The invention relates to read only memory (ROM) circuits that employ metal-oxide-semiconductor (MOS) devices. In such circuits, an array of transistors is configured into rows and columns that can be selectively addressed so that each transistor in the array can be connected to the output circuit. During manufacture transistors are built into the array in a pattern that will provide the desired data. Where a transistor is present, a logic one is stored and the absence of a transistor indicates a stored logic zero. Thus, in the transistor making stage of manufacture the customer-determined logic is located in the ROM as a particular pattern of transistors. This pattern is located in what is called the memory-array section which is accessed and/or read using a peripheral section array of transistors interconnected to provide the desired functions.
One of the peripheral section array functions is the sense amplifier which can take the form disclosed in my copending application Ser. No. 391,255 filed June 23, 1982. This application which is titled Current Difference Sense Amplifier is assigned to the assignee of the present application, is now U.S. Pat. No. 4,464,591, which issued Aug. 7, 1984, and is incorporated herein by reference.
In semiconductor integrated circuit (IC) designs, the MOS approach is employed to create chips that have multiple individual components. These commonly employ the so called N channel field-effect transistor (FET) devices. Metal-gate device construction has been developed into a reliable high-speed low-cost form of construction that is highly suited to making ROM devices.